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zuyuan
- 这是一个实现有限状态机的verilog编程的程序-This is a realization of finite state machine programming procedures verilog
zhuangtaiji
- 检测姓名序列的状态机。使用VERILOG编写。平台是QuartusII9.1。Cyclone -Detection of sequence state machine name. Prepared using VERILOG. Platform is QuartusII9.1. Cyclone III
lsh
- 基于Verilog的状态机的流程图及源代码-Verilog state machine based on the flow chart and code
statemachine
- 状态机可以实现几个状态之间的转换,这时使用qt编写的verilog文件-statemachine for inter change between any one of them
iiscode
- 用Verilog写的一个简单的IIs控制器，分为clkgen时钟分频模块和transcon传输控制模块。其中transcon模块主要部分为一个有限状态机实现的满足IIS标准的输出。 另附一个简单的Testcase以及得到的波形。-Develop an iis controller with verilog hdl. The key parts of iis were departed in two. One is clkgen.v which generate the clk and syn
1602LCD
- 该程序是1602的verilog程序，该程序采用状态机编写-The program is 1602' s verilog program, the program prepared by the state machine
ywjc
- 采用状态机的方法实现移位寄存器，用Verilog HDL编写，已经通过验证。-The method uses the state machine implementation shift register, with write Verilog HDL has been verified.
xinjiaotong
- 自己编写的，使用Verilog语言辨析的在FPGA上实现的交通灯的红绿黄灯，用状态机实现，共有六种状态，红-绿、红-黄、左转弯、绿-红、黄-红、左转弯，每种状态配以数码管显示区分。-I have written, use the Verilog language Discrimination implemented in the FPGA, red, green and yellow traffic lights, a total of six states, red- green, red-
zidongshouhuojisheji
- 本文采用Verilog HDL描述语言实现自动售货机系统的销售动作，用有限状态机进行系统状态描述，自动售货机通电复位时，自动进入系统初始状态，本文设计的自动售货机控制系统主要可以实现投币处理、计算投币总额、输出商品，输出找零、余额计算并显示等功能。-This verilog hdl describe language used for automatic machines system of action, with a limited system of state, state, the v
zhuangtaiji
- 状态机的使用 verilog】 真的就这么多了-verilog
data_check_hand_in
- 一个基于状态机的8位码流检测实现，Verilog语言，在ISE 10.1环境下编译通过。-A state machine-based 8-bit code stream detection to achieve, Verilog language, the ISE 10.1 environment compile.
FSM
- 有限状态机，用Verilog语言，执行正确，仿真通过。-Finite state machine, with the Verilog language, the implementation of the right, simulation pass.
rom_con_aa
- VERILOG 多线程控制程序，实现状态机控制ad采集-VERILOG multi-threaded control program, to achieve a state machine control ad acquisition
statemachine
- RTL级verilog代码 用状态机实现 将输入数据写入16位寄存器，输出其除以7所得的余数（4位）-RTL-lever verilog code Using FSM to realize the following function:input the data into a 16bit register, divide it by 7, and output the 4-bit remainder
traffic_light
- 用Verilog HDL语言写一个交通控制灯的状态机。十字路口，红绿灯，带倒计时功能，也可以自行变换亮灯时间。-Verilog HDL language used to write a traffic control light state machine. Intersections, traffic lights, with the countdown function, you can also change their own light time.
caideng
- 这个程序是用verilog语言编写的彩灯的小程序，使用状态机来实现，可以实现多种花型，有具体的程序！-This program is written in verilog small lantern, the use of state machine, you can achieve a variety of flowers, there are specific procedures!
chuzuche
- 本程序使用verilog语言编写的出租车计价系统，实现时距并计！主要用状态机来实现！-This program uses the taxi meter verilog language system, and taking into account the time-distance! State machine is mainly used to achieve!
yinliao
- 本程序采用verilog语言编写实现仿真自动饮料机的功能，采用状态机来实现！-This procedure uses verilog language automatic beverage machine emulation capabilities, the use of state machine!
state_machine
- 基于FPGA用VHDL编写的状态机控制步进电机.-Prepared by the state machine control VERILOG stepper motor.
STATE_MECHINE
- FPGA 状态机控制步进电机..verilog-FPGA state machine controlled stepper motor .. verilog